Electrical communication architectures struggle to balance the dichotomy for increased performance required of electronic systems while addressing lower power consumption, smaller form factor, and lower electromagnetic emissions. Better solutions dealing which address scalability while reducing power consumption in computer systems is desirable. A memory system is an example of a typical computer system in which such better solutions are desirable.
Some current computer memory systems use a wide parallel bus to communicate with bulk memory. With increasing memory densities and memory bus speeds, the bus widths and speeds must also be increased. This parallel bus architecture has reached a point where it can no longer scale with the demands of current and future multi-core microprocessors.
In a typical example of bulk memory using Dual In-line Memory Module (DIMM) technology with a series of Dynamic Random Access Memory (DRAM) integrated circuits in each DIMM mounted on a printed circuit board (PCB), the electrical problem of scaling the high-speed parallel bus to wider widths and speeds limit the maximum number of DIMMs per channel. For example, DDR3 channels which can operate up to an effective clock rate of 400-800 MHz can only support a single DIMM.
An alternative technology, the Fully Buffered DIMM (FBDIMM) addressed this scalability issue by replacing the wide parallel bus with narrow serial point-to-point links between the memory controller and an intermediate memory buffer within each FBDIMM module. This intermediate memory buffer called an Advanced Memory Buffer (AMB) communicates with the memory controller, and also replicates and forwards data to an adjacent AMB in the next FBDIMM. The AMB is also responsible for converting the serialized data to the parallel data needed to communicate with the DRAMs. The serial interface is split into two uni-directional buses, one southbound for command, address and write data and one northbound for read data. However, the daisy chaining or point-to-point configuration is problematic as the hops introduce latency. The need to replicate and forward both northbound and southbound signals adds latency, eventually leading to bottlenecks. The AMBs also consume a large amount of power due to the need to send the high speed electrical signals between AMBs and the serialization and deserialization of data from the DIMMs. A multicast or broadcast architecture would be more desirable.
These examples illustrate that, as the speed of communication in electrical systems has increased, signal integrity issues have limited electrical communication memory interconnects to point-to-point interconnects. What is desired is a low power system providing high speed interconnects that maintains signal integrity and which can also support lower latency topologies with multiple receivers (fan-out) connected to one or more drivers, or systems with multiple drivers (fan-in) connected to one or more receivers. Such qualities are desired in other types of computer systems as well.